Silicon and Heterogeneously Integrated Photonics Towards Sub-pJ/bit, Multi-Tbps Optical I/O and Next-Generation AI Clusters
Description:
As AI/ML compute clusters scale toward hundreds of thousands of accelerators, inter-chip communication bandwidth is experiencing unprecedented exponential growth, pushing traditional copper-based electrical interconnects and conventional digital signal processing (DSP)-heavy optical transceivers to their physical limits in energy consumption, thermal dissipation, and edge density. To break through the looming "power wall" and "bandwidth density bottleneck," the optical communications industry is accelerating its paradigm shift from linear-drive pluggable optics (LPO) toward co-packaged optics (CPO) and near-chip, die-level Optical I/O. This workshop focuses on revolutionary architectural and device-level breakthroughs across material platforms, native on-chip sources, high-speed modulation, and zero-power static tuning, aiming to achieve multi-Tbps per waveguide physical-layer optical interconnects under a strict sub-1 pJ/bit energy budget. The technical scope mainly encompasses: high-yield integration of quantum-dot lasers and microcombs on standard silicon photonics foundries to eliminate external laser coupling losses; sub-volt, ultra-high-bandwidth thin-film lithium niobate (TFLN) modulators based on rings and photonic crystal nanobeam cavities to enable DSP-less host ASIC/SerDes direct drive; and monolithic back-end-of-line non-volatile phase-change material (PCM) integration for post-fabrication phase correction and static power elimination. By cascading active high-efficiency devices with passive multi-dimensional multiplexing, this symposium will bridge pioneering micro-and-nanophotonics physics with commercial foundry mass-producibility, mapping out the definitive energy-efficient, high-throughput all-optical networking infrastructure.
Time: TBD
Venue: TBD
Organizers:
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Speakers:
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